1. Field of the Invention
The present invention relates to a field effect semiconductor device, and more particularly to a field effect semiconductor device having a metal-oxide-semiconductor (MOS) structure in a semiconductor layer which is one of its constituents.
2. Description of the Background Art
A MOS semiconductor device is often used for a switching element because of its operation driven by voltage and relatively easy high-speed switching. FIGS. 15 and 16 show an example of a prior-art power MOSFET which is one of MOS semiconductor devices. FIG. 15 is a view showing a pattern of impurities formed in a surface of a semiconductor layer when viewed from its front-surface side of the power MOSFET, and FIG. 16 is a schematic section taken along the line A--A of FIG. 15. In FIG. 15, a gate electrode 6, an interlayer insulating film 7 and a source electrode 8 of FIG. 16 are omitted.
In the power MOSFET having the above structure, an n.sup.- semiconductor region 2 is formed in an n.sup.+ semiconductor substrate 1. The n.sup.- semiconductor region 2 is a constituent of the semiconductor layer. The n.sup.- semiconductor region 2 is, for example, an epitaxial layer. A plurality of p-type diffusion regions 3 are arranged like islands in a surface of the n.sup.- semiconductor region 2, in other words, a one-side major surface of the semiconductor layer. The P-type diffusion region 3 has a planar shape of substantial square and a section of reverse-dome shape (downward convex) with flat bottom. Inside a surface of the p-type diffusion region 3, an n.sup.+ source region 4 is formed. The n.sup.+ source region 4 has a planar shape of rectangular ring and a substantially rectangular section. The n.sup.+ source region 4 is covered with the p-type diffusion region 3 on the side of the semiconductor layer in order to serve as an FET. A gate insulating film 5 is so formed as to cover the surface of the p-type diffusion region 3 between the n.sup.+ source region 4 and the n.sup.- semiconductor region 2 and the surface of the n.sup.- semiconductor region 2. In other words, the gate insulating film 5 is formed on the one-side major surface of the semiconductor layer above a channel region 10 between the annular peripheral portion of the annular n.sup.+ source region 4 and the peripheral portion of the p-type diffusion region 3 which are adjacent to each other. On the gate insulating film 5 formed is the gate electrode 6 having almost the same planar shape as the gate insulating film 5. As a material of the gate electrode 6, for example, polysilicon is used. The interlayer insulating film 7 is so formed as to cover the gate electrode 6. The surface of the p-type diffusion region 3 inside the annular n.sup.+ source region 4 and a portion of the surface of internal circumference side of the n.sup.+ source region 4 are not covered with the interlayer insulating film 7. Since the source electrode 8 is deposited entirely on the one-side major surface of the semiconductor layer including above the interlayer insulating film 7, the source electrode 8 is in contact with the portion of the n.sup.+ source region 4 which is not covered with the interlayer insulating film 7 and the p-type diffusion region 3 surrounded by the n.sup.+ source region 4 on the one-side major surface of the semiconductor layer 100.
In the power MOSFET having the above structure, when a positive gate voltage is applied to the gate electrode 6 while applying a drain voltage such that the potential of the drain electrode 9 may become positive relative to the potential of the source electrode 8, the polarity of the surface of the p-type diffusion region 3 between the n.sup.+ source region 4 and the n.sup.- semiconductor region 2 is reversed into n type, creating a channel in the channel region 10. In this state, an electronic current flows through the n.sup.+ source region 4 and the channel region 10 into the n.sup.- semiconductor region 2, to bring the power MOSFET into conduction.
An on-resistance of this power MOSFET is classified into, for example, resistance elements as shown in FIG. 17. Reference signs given to the resistance elements of FIG. 17 are also used to represent values of the resistance elements. In FIG. 17, Rn.sup.+ represents the resistance element of the n.sup.+ source region 4, Rch represents a channel resistance element, Rac represents an accumulation resistance element of the silicon surface, Rj represents the resistance element of a junction FET (J-FET, thereafter) formed between the p-type diffusion regions 3 of adjacent MOS unit cells, Repi represents the resistance element of the n.sup.- semiconductor region 2 and Rsub represents the resistance element of the n.sup.+ semiconductor substrate 1. The MOS unit cell refers to a structure including only one p-type diffusion region 3 existing like an island to serve as a MOSFET. When the on-resistance of the power MOSFET is represented as Ron, the on-resistance Ron is obtained from Formula 1: EQU Ron=Rn.sup.+ +Rch+Rac+Rj+Repi+Rsub (1)
In order to reduce the on-resistance of the power MOSFET, it is necessary to lower the resistance elements of Formula 1. To lower the channel resistance element Rch, it is effective to increase a channel width. To increase the channel width, it is effective to increase the cell density of the MOS unit cell with size reduction of the p-type diffusion region 3.
FIG. 18 is a schematic section showing a prior-art vertical MOSFET shown in, for example, Japanese Patent Application Laid Open Gazette 3-70387. To lower the resistance element Rj of the J-FET formed between the p-type diffusion regions 3, as shown in FIG. 18, it is effective to form an n.sup.+ diffusion region 12 between the p-type diffusion regions. The prior-art n.sup.+ diffusion region 12 is formed on the periphery of a region in which a plurality of MOS unit cells are disposed. Providing the n.sup.+ diffusion region 12 produces an effect of reducing the spacing between the p-type diffusion regions 3 without increasing the resistance element Rj, by which the channel resistance element Rch can be lowered.
FIG. 17 also shows an equivalent circuit model of the MOS unit cell. Elements constituting the equivalent circuit model will be described below with reference to FIG. 17. A parasitic npn transistor exists therein, consisting of the n.sup.+ source region 4, the p-type diffusion region 3 and the n.sup.- semiconductor region 2. The base of the parasitic npn transistor is connected to the source electrode 8 through a diffusion base resistance Rb. The emitter of the parasitic npn transistor is connected to the source electrode 8 through the resistance element Rn.sup.+ of the source region 4. The resistance element Rn.sup.+ of the source region 4, together with the channel resistance element Rch, the accumulated resistance element Rac, the resistance element Rj of the J-FET, the resistance element Repi of the n.sup.- semiconductor region 2 and the resistance element Rsub of the semiconductor substrate 1 which are connected in series to the resistance element Rn.sup.+, constitutes the resistance element Ron of the power MOSFET. Representing a potential difference between the n.sup.+ source region 4 and the p-type diffusion region 3, an avalanche current and a diffusion base resistance immediately below the n.sup.+ source region 4 as Vb, Jb and Rb, respectively, when the condition of Formula 2 is satisfied, the n.sup.+ source region 4 and the p-type diffusion region 3 are brought into a forward bias state, to bring the parasitic npn transistor into conduction. EQU Vb=Jb.times.Rb.gtoreq.about 0.6V (2)
To turn off the power MOSFET, it is necessary to bring the gate electrode 6 into the same potential as that of the source electrode 8 or a negative potential. At this time, the magnitude of a voltage to be applied across the source electrode 8 and the drain electrode 9 depends on the voltage breakdown resistant characteristics of a diode formed in the p-type diffusion region 3 and the n.sup.- semiconductor region 2. A breakdown of the power MOSFET causes the avalanche current to flow.
When the parasitic npn transistor becomes conducting, a current flows locally, which breaks down the power MOSFET. To prevent conduction of the parasitic npn transistor, it is effective to reduce the avalanche current Jb and lower the diffusion base resistance Rb. To reduce the avalanche current Jb, there is a method of preventing formation of a path for the avalanche current immediately below the n.sup.+ source region 4. Not to flow the avalanche current immediately below the n.sup.+ source region 4, it is effective to form a p-type diffusion region 11 deeper than the p-type diffusion region 3 as shown in FIG. 18. The depth of the n.sup.+ diffusion region 12 is determined shallower than a lower portion of the p.sup.+ diffusion region 11. In other words, the n.sup.+ source region 4 is connected to the n.sup.- semiconductor region 2 through the p-type regions surrounding the n.sup.+ source region 4, i.e., the p-type diffusion region 3 and the p.sup.+ diffusion region 11. In order to lower the diffusion base resistance Rb, it is effective to increase the concentration of the p-type diffusion region 3 or form another high-concentration p-type diffusion region inside the p-type diffusion region 3.
Japanese Patent Application Laid Open Gazette 8-227993 shows a technique to improve a withstand avalanche voltage with a structure different from the above.
In a switching device like the power MOSFET, to promote energy savings and simplification of circuit design, it is desirable that the loss of energy of the device on switching or in an on state should be as small as possible. Therefore, reduction in switching loss and on-resistance is the most critical issue for the switching device.
Now studied will be on reduction of on-resistance by lowering the resistance elements Rj and Rch. As discussed earlier, one of the methods for lowering the resistance elements Rj and Rch is to form the n.sup.+ diffusion resistance 12 in the surface of the n.sup.- semiconductor region 2. Relations shown in FIG. 19 are held between the amount of phosphorus injected for forming the n.sup.+ diffusion region 12 and the on-resistance Ron and between the spacing between the p-type diffusion regions 3 and the on-resistance Ron. Specifically, as the concentration of the n.sup.+ diffusion region 12 becomes higher, the on-resistance Ron becomes lower and as the spacing between the p-type diffusion regions 3 becomes wider, the on-resistance Ron becomes lower.
On the other hand, widening the spacing between the p-type diffusion regions 3 and increasing the amount of phosphorus injected for forming the n.sup.+ diffusion region 12 cause a decrease of the withstand voltage. FIG. 20 shows relations between the amount of phosphorus injected for forming the n.sup.+ diffusion region 12 and the withstand voltage V.sub.DSS and between the spacing between the p-type diffusion regions 3 and the withstand voltage V.sub.DSS. As the amount of phosphorus injected for forming the n.sup.+ diffusion region 12 increases, the withstand voltage V.sub.DSS decreases. As the spacing between the p-type diffusion regions 3 is widened, the withstand voltage decreases, and this tendency becomes more pronounced as the amount of injected phosphorus increases. This phenomenon results from that an electric field strength is increased by widening the spacing between the p-type diffusion regions 3 and increasing the amount of injected phosphorus. Because of the need for ensuring a desired withstand voltage, the spacing between the p-type diffusion regions 3 should not be indiscriminately widened and the amount of injected phosphorus should not be indiscriminately increased. Therefore, it is necessary to determine the spacing between the p-type diffusion regions 3 and the amount of phosphorus injected for forming the n.sup.+ diffusion region 12 in consideration of both the withstand voltage and the on-resistance.
In the prior-art field effect semiconductor device, the impurity concentration of the n.sup.+ diffusion region 12 is determined uniform in the surface of the semiconductor layer though it is determined in consideration of the trade-off relation between the withstand voltage and the on-resistance as discussed above. For example, as shown in FIG. 15, even if the spacings between the MOS unit cells, i.e., the spacings a and b between the p-type diffusion regions 3, are different since the MOS unit cells are polygons in the power MOSFET, the impurity concentration of the n.sup.+ diffusion region 12 is determined in accordance with the spacing b lest the withstand voltage should decrease in the wider spacing b. For this reason, the relation between the withstand voltage and the on-resistance is not optimal in the spacing a.
In some cases, in order to prevent the parasitic npn transistor from turning on when the avalanche current flows in the power MOSFET, the p-type diffusion region 11 is formed near the center of a lower portion of the p-type diffusion region 3 so as to be deeper than the lower portion of the p-type diffusion region 3 as discussed with reference to FIG. 18. An influence of the p-type diffusion region 11 on the on-resistance will be discussed with reference to FIGS. 21 to 23. FIGS. 21 to 23 show simulations of the on-resistance of the a 60 V-system power MOSFET. In FIGS. 21 to 23, lines with the reference signs J1 to J12 are equivalent current density lines and a reference sign of larger number represents a higher current density. In FIGS. 21 to 23, the equivalent current density lines with the same reference sign show the same current density. The power MOSFET of FIGS. 21 to 23 have the same structural conditions except existence of the p-type diffusion region 11 and its depth. From FIGS. 21 to 23, it can be seen that a relatively high current density is distributed up to near the center of the lower portion of the p-type diffusion region 3. From these figures, it can be also seen that the p.sup.+ diffusion region 11 has an effect on an electron density distribution as it becomes deeper and when the p.sup.+ diffusion region 11 exists or it is deepen, a range for high current density distribution is narrowed to increase the on-resistance. Though the p-type diffusion region 11 is formed near the center of the lower portion of the p-type diffusion region 3 for the purpose of improving the withstand avalanche voltage in the prior art, forming the p.sup.+ diffusion region 11 has an ill-effect on the on-resistance, increasing the on-resistance.